In this project we are going to implement different circuit configurations of D-flip flop which is most commonly used flip flop in digital circuits. They are positive edge triggered or negative edge triggered of clock. Flip flops store data and update it depending upon the input clock. The basic difference between latches and flip flops is that latches are asynchronous which means they change the data as soon as the input of the circuits changes, whereas flip flops are synchronous or clock operated. we will implement following types of D-flip flop in DSCH simulation software first. In sequential digital circuits Latches and flip flop are two very common types of circuits that are used. So in this paper first of all we will analyze the implementation of D-flip flop in DSCH software.

We have tried to optimize our layouts as maximum as possible. At the end layout of different types of D Flip-Flops is designed using microwind software. We have verified the output of different types of Flip flops using these simulation softwares. Xilinx ISE is used to write verilog code and simulate results. DSCH is used for logical simulation of different types of D Flip-Flops and Hardware description language verilog is also used for logical verification. The main objective of this paper is study and analyze different types of Flip flops and design their physical layouts. Flip Flop is basically a device which maintains its state until positive or negative edge of clock triggered. Optimized Design and simulations of D-Flip Flop using DSCH3, Xilinx ISE & Microwind: In this article we have studied the simulation, verilog verification and physical layout design of D Flip-Flops using different simulation softwares.

Microwind software